Electrostatic clamps or chucks (ESCs) are often utilized in the semiconductor industry for clamping substrates during plasma-based or vacuum-based semiconductor processes such as etching, CVD, and ion implantation, etc. Capabilities of the ESCs, including non-edge exclusion and wafer temperature control, have proven to be quite valuable in processing semiconductor substrates or wafers, such as silicon wafers. A typical ESC, for example, comprises a dielectric layer positioned over a conductive electrode, wherein the semiconductor wafer is placed on a surface of the ESC (e.g., the wafer is placed on a surface of the dielectric layer). During semiconductor processing (e.g., ion implantation, plasma processing, etc.), a clamping voltage is typically applied between the wafer and the electrode, wherein the wafer is clamped against the chuck surface by electrostatic forces.
A subset of electrostatic clamps, referred to as Johnsen-Rahbek (J-R) clamps, utilize “leaky” dielectric layers (e.g., semiconductive dielectric layers having bulk resistances of between approximately 1×109 to 1×1012 Ohm-cm) in contact with the wafer, wherein greater clamping forces can be achieved at lower voltages than with conventional Coulombic clamps. Lower voltage input to the ESC typically not only reduces power supply requirements associated with the J-R clamps, but further provides a clamping environment that is potentially less destructive to the wafer and devices formed thereon.
A conventional J-R clamp, for example, comprises a dielectric layer that is slightly conductive, thus generally permitting a thickness of the dielectric layer (e.g., a ceramic) to be much thicker than would be permitted for a “classic” or Coulombic ESC. Such an increase in thickness greatly facilitates the clamp manufacturing process, while also reducing clamp operating voltages. For example, the dielectric layer can be used as a base for the formation of positive and negative electrodes by screen printing and firing of a dielectric paste.
In some applications, processing of the wafer can occur at low temperatures (e.g., −50 C), while in other applications, processing of the wafer can occur at higher temperatures (e.g., 150 C). Conventionally, a single J-R clamp, however, cannot accommodate both extremes of temperature, as the resistivity of the dielectric layer changes with temperature. Thus, the clamping force exhibited by a conventional J-R clamp varies dramatically with temperature, thus yielding potential undesirable clamping effects.